RE: [sv-bc] Mantis 1602: task/function default inout arguments

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Jul 17 2007 - 09:24:31 PDT
When Verilog was first implemented, there was no such thing as separate
compilation.

Shalom
 

> The reason port width mismatch warnings/errors are 
> issued only for modules is that the module/endmodule is 
> typically the boundary in separate compilation.

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Received on Tue Jul 17 09:25:11 2007

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