Hi, > A Verilog function is syntactic sugar for a combinational > module. That is only in synthesizable RTL, but functions have many uses in Verilog, including testbenches, and functions predate synthesis anyway. Not to mention tasks, which are certainly not "syntactic sugar for a combinational module". Shalom -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 17 08:54:30 2007
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