[sv-bc] LRM port declaration sections

Hi, 

I renamed this thread to reflect the change in subject.

> In fact, Steve's change to 1800-2005 made the port definition 'input
> logic a;' actually default to the wire kind. See 22.2.2.3 Aggregate
> ports. BTW, I think this section is improperly titled. It should be
> something like "Additional port features"

I think the name 'Aggregate ports' comes from the first sentence of the
subsection:

"A port can be a declaration of an interface, an event, or a variable or
net of any allowed data type, including an array, a structure, or a
union."

But that is really the only sentence in this subsection that talks about
aggregate ports, so I think this is not the place for it.

I think that sentence should move to 22.2.2.

I would rename 22.2.2.3 to something like "Default port types and
directions" or "Implicit declaration of port types and directions" or
"Rules for determining port types and directions".

I also think that the last paragraph in this subclause,

"Generic interface ports cannot be declared using the non-ANSI list of
ports style (see 22.2.2.1). Generic interface ports can only be declared
by using a list of port declaration style.
module cpuMod(interface d, interface j);
...
endmodule"

also does not belong here and should move to 22.2.2.2. (Mantis 1597
modifies the text of this paragraph.)


Shalom

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