[sv-bc] minor wire issues

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Mon Jul 02 2007 - 02:42:08 PDT
  

Hi,

A few minor issues related to tri's and uwire's.

1. 6.8.1 has the example: tri [15:0] busa; // a three-state 16-bit bus
This is not accurate. tri is exactly the same as wire. It may or may not
be three-state.

 

2. 6.10.1 describes tri and wire. 
6.10.2 describes wired-and and wired-or nets. 
6.10.3 describes triregs. 
6.10.4 describes tri0 and tri1. 
6.10.5 describes uwires.

I think uwires are closer to plain wires than any of those other
variants, so I think the uwire sub-clause should immediately follow
6.10.1 instead of being several sub-clauses distant.

 

3. 10.3.4 Continuous assignment strengths

The driving strength of a continuous assignment can be specified by the
user. This applies only to assignments

to scalar nets of the following types:

wire tri trireg

wand triand tri0

wor trior tri1

This omits uwires. In fact, it would be easier to write

This applies only to assignments to scalar nets, except of type supply0
and supply1.

 

4. Annex L: vpiTri has the comment /* three-state net */. This is not
accurate. tri is exactly the same as wire. It may or may not be
three-state.

 

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033 

 


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Received on Mon Jul 2 02:43:24 2007

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