Date: Wed Jun 06 2007 - 02:34:33 PDT
Hi, The following sentence at the end of the third paragraph in 6.7 is an error: "A variable cannot be written through a port; it must go through an implicit continuous assignment to a net." This sentence comes a paragraph in 1800-2005 which is describing Verilog and the next paragraph there describes the SV extensions. This sentence should be deleted. Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
