[sv-bc] {Disarmed} Mantis 1852: Ballot Feedback Issue STU2: Declarations on Assertions

 
 
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ID: 	Category: 	Severity: 	Reproducibility: 	Date
Submitted: 	Last Update: 	
1852 	SV-AC 	feature 	always 	06-04-07 14:32 	06-04-07 14:32 	
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Reporter: 	pieper 	Platform: 		 	
Assigned To: 		OS: 		 	
Priority: 	normal 	OS Version: 		 	
Status: 	new 	Product Version: 		 	
Product Build: 		Resolution: 	open 	 	
Projection: 	none 	Duplicate ID: 		 	
ETA: 	none 	 	
Type: 	Errata 	
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Summary: 	Ballot Feedback Issue STU2: Declarations on Assertions 	
Description: 	The following feedback was raised as a ballot issue in
the 2005 ballotting:

Clause 18 on assertions is ambiguous as to whether identifiers must be
declared prior to being referenced in a property or sequence block. Some
existing implementations require the declaration come first, and some do
not. It is my understanding that Verilog allows identifiers to be
referenced prior to declaration in specify blocks, tasks, and functions.
If this is correct, then it would be reasonable for users to expect that
property and sequence blocks be consistent with that rule. Allowing
reference before declaration might also help with binding externally
declared properties and sequences to a design block. In either case, the
P1800 LRM should explicitly state the rule of order for declaration
versus reference in a property or sequence block. The current ambiguity
has lead to code that is not portable across multiple tools. 

This issue was addressed in the balloting by:

The committee read and considered this feedback. While it
has merit, the committee believes it is either not feasible to implement
at this time or not in the scope or goals of the P1800 project as it was
defined & agreed upon by the P1800 WG

I'm reopening the issue to make sure we discuss it prior to ballot in
2008. 	
Steps To Reproduce: 	See above 	
Additional Information: 	None 	
Attached Files: 		

There are no notes attached to this bug. 	

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