Re: [sv-bc] string == and !=

Hi Geoffrey,

This mantis item on strings probably belongs in the svec.
Thanks for putting together a proposal.


Neil



Geoffrey.Coram wrote On 04/23/07 06:58,:
> I've opened a mantis item and uploaded a proposal:
> http://www.eda-stds.org/mantis/bug_view_page.php?bug_id=0001789
>  
> 
> "Geoffrey.Coram" wrote:
> 
>> I just got a look at 1800D2; the Table that needs the changes below is
>> now numbered Table 7-2.
>>
>> I also want to comment on this paragraph from the previous page:
>>   A string literal can be assigned to a string type or an integral
>> type. If their sizes differ,
>>   the literal is right justified and either truncated on the left or
>> zero filled on the left,
>>   as necessary.
>>
>> The second sentence needs to make clear that it's only an integral
>> type that gets truncated or zero-filled; a string type is dynamically
>> sized.
>>
>> -Geoffrey
>>  
>>
>> "Geoffrey.Coram" wrote:
>>
>>> I'd like to propose a slight wording change to the first and third
>>> rows in Table 4-2 (String operators):
>>>
>>> /Equality/. Checks whether the two strings are equal. Result is 1 if
>>> they are equal and 0 if they are not. Both strings can be of type
>>> *string*. Or, or one of them can be a string literal which is
>>> implicitly converted to a string type for the comparison. If both
>>> operands are string literals, the operator is the same Verilog
>>> equality operator as for integer types.
>>>
>>> /Comparison./ Relational operators return 1 if the corresponding
>>> condition is true using the lexicographical ordering of the two
>>> strings Str1 and Str2. The comparison uses the compare string method.
>>> Both operands can be of type *string*, or one of them can be a string
>>> literal which is implicitly converted to a string type for the
>>> comparison.
>>>
>>> The entries in rows 4 and 5 are explicit about conversions for
>>> replication and concatenation; I think it makes sense also for
>>> equality and comparison.
>>>
>>> -Geoffrey
>>>
> 

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