RE: [sv-bc] MERGE REVIEW draft 2: Chapter 10

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Wed Apr 11 2007 - 04:15:07 PDT
No. This 1364 restriction is no longer true in 1800. Stu knows this, but
must have forgotten it, or simply did not notice this sentence. 

The problem is that 1800 is not explicit about this.

See http://www.eda-stds.org/sv-bc/hm/4730.html and Mantis 1555.

Shalom


> 10.4 "Variable declaration assignments are only allowed at the module
> level."  So the declarations of j and k below are illegal?
> 
>     function automatic f(input int i);
>        int j = 0;
>        ...
>     endfunction
> 
>     always @(posedge clk) begin
>        int k = 0;
>        ...
>     end

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Received on Wed Apr 11 04:15:50 2007

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