[sv-bc] MERGE REVIEW draft 2: Chapter 10

10.1, Table 10-6 --

   Why this mention of "vector net or packed variable"?  Couldn't the
left-hand side of a continuous assignment be a bit- or part-select of a
net or variable with an unpacked type?  Or is the claim that the
following example is illegal?

   typedef int T[3];

   wire T w;
   var T v;

   assign w[0:1] = '{10,20};
   assign w[2] = 30;

   assign v[0] = w[2];
   assign v[1:2] = w[0:1];


10.2.2 "or module output,."  Extra comma.


10.3 "variable type on left-hand side"  --> "variable type on the
left-hand side"


10.3.2 "The order of evaluation of the variable_lvalue and the
expression on the right-hand
side is undefined."  This eliminated "if timing control is not
specified".  I don't know whether the change is correct or not, but
removing the 'if' phrase seems to yield a significant difference in the
meaning of the sentence.  And it wasn't removed from a similar sentence
in 10.3.1.  Why was this phrase only wrong for nonblocking assignments?


10.4 "Variable declaration assignments are only allowed at the module
level."  So the declarations of j and k below are illegal?

    function automatic f(input int i);
       int j = 0;
       ...
    endfunction

    always @(posedge clk) begin
       int k = 0;
       ...
    end


10.6 "Implementations can, but are not required to, warn or report any
errors related to assignment size mismatch or truncation. Size casting
can be used to prevent these warnings"  This seems to be disallowing
warnings about size casts that discard MSBs.  I don't think the LRM
should be disallowing warnings about anything.

-- Brad



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