[sv-bc] uninstantiated interface/program

In Verilog, a module that is not instantiated anywhere in the design
is implicitly instantiated as a top-level module.  Is this supposed
to occur in SV for interfaces and programs also?  Or are these only
supposed to be instantiated explicitly?

I recognize that some tools offer options to explicitly specify the
top-level modules, instead of using this implicit rule.  But when the
implicit rule is applied, does it apply to interfaces and programs?

Steven Sharp
sharp@cadence.com


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