Mark Hartoog wrote: >> For example, you can have tasks in interfaces that are used >> to access the objects in the interface. These tasks can be >> called from different modules where the interface has been >> passed. If passing the interface is making copies of the >> objects in the interface, then which object is the task >> supposed to access? Does it access the copy that is visible >> to the module doing the call? I am not sure how that would >> be implemented, and it probably wouldn't have the expected >> behavior. > > Consider this case: > > module interf; > integer x; > task print(); > $display("x = ", x); > endtask > endmodule > > module child(output integer o); > initial > begin > o = 5; > top.interf.print(); > end > endmodule > > module top; > interf interf(); > child child(interf.x); > endmodule > > What value will this print? Are there Verilog simulators where this > will not print '5'? I don't know whether there "are" or not, but if the connect from the output to the "x" is in fact a continuous assign, it is certainly valid for a simulator to not print "5". There is no guarantee at all that continuous assigns activate prior to the call maturing. Now if you make the port a "ref" then you do have a guarantee but then Steven's question is more apropos -- is the "x" in fact the same "x"? If so then a simulator must produce "5"; if not, I would also be worried about the semantics. Gord. -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Feb 27 14:20:55 2007
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