RE: [sv-bc] Are modport port directions enforced?

>From: "Mark Hartoog" <Mark.Hartoog@synopsys.com>

>When you instantiate the module, there is an implicit continuous
>assignment to the input port. If there is another continuous or
>procedural assignment inside the module to the port, then that violates
>the one continuous assignment or one or more procedural assignment rules
>for variables. This is covered in section 6.7 and 11.5.

Mark,

Are you actually suggesting that an interface passed through hierarchy
will create an implicit continuous assignment for each port that it
is passed through, for any object declared in a modport? 

If so, are you suggesting that there is an implicit continuous assign
between the interface and each module that references it, existing in
parallel?  Each module would be making a copy of the original variable
in the interface.  Or are you suggesting that there is an implicit
continuous assignment in series at each port that the interface passes
through, as there would be for a variable passed through a port without
the interface?  Each module would be making a copy of the variable that
its parent used, which might be a copy of its parent's version, etc.

Neither of these fits my understanding of interfaces.  My understanding
was that all these modules were accessing the exact same variable: the
original one in the interface.  It seems pretty clear that this is how
an interface without modports behaves.  It was my understanding that a
modport simply restricted access, rather than changing the entire
mechanism by which the interface was accessed.

If the accesses to variables in the interface are to the original
variable, then there is no implicit continuous assignment.  A write to
the variable would be a write to the original variable, not to a copy
that is being driven by an implicit continuous assignment.  If there
are no explicit continuous assignments to the original variable anywhere,
then that write would be perfectly legal by the LRM.

Steven Sharp
sharp@cadence.com


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