RE: [sv-bc] implicit net declarations on ports

I like Shalom's suggestion.  Syntactically, it would be easy to add a
"ports_only" or similar argument to `default_nettype.  This feature would be
a very useful compromise between the convenience of inferred nets and the
risks of unintentionally inferred nets.  

A semantic change is required for this enhancement.  Currently, any
`default_nettype overrides any previously specified `default_nettype
directive.  For "`default_nettype ports_only", it should just modify any
previous directive.  So, for example, I should be able to do:

  `default_nettype pull1
  `default_nettype ports_only
   module foo (input [7:0] a, output [7:0] b);
   ...

Taking this one step further, I think this extension would become even more
useful if it also modified the .name and .* constructs, which currently
require explicit net (or variable) declarations.  The rule should be added
that a net inferred from an explicitly named module port will be connected
to port instances of the same name, provided all rules for the inferred
connection are met.  

This, however, would be a bigger change, and might have backward
compatibility issues.  Currently implicit nets are NOT inferred from port
declarations, but from port instance connections (or the LHS of continuous
assigns).  Since .* and .name do not explicitly name a signal, no net is
inferred, even when the identifier is in the containing module's port list.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom
> Sent: Monday, February 19, 2007 8:20 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] implicit net declarations on ports
> 
>  
> 
> Using Verilog-1995 port declaration syntax, we say that
> 
> module m(a);
> 
> input a;
> 
> endmodule
> 
> creates an implicit net declaration of a.
> 
> Thus, if I write
> 
> `default_nettype none
> 
> then I get an error message that a does not have a net declaration.
> 
> The same occurs if I write
> 
> `default_nettype none
> 
> module m(input a);
> 
> though I think the LRM is a little ambiguous about that.
> 
>  
> 
> It is common methodology to allow implicit net declarations 
> of ports, since the name is already declared as part of a 
> port and thus not completely undeclared, and the additional 
> net declaration is redundant. At the same time, other 
> implicit declarations are forbidden in many of those methodologies.
> 
> The problem is that today `default_nettype does not support 
> allowing implicit net declarations of ports while not 
> allowing other implicit net declarations.
> 
> I would like to see this added.
> 
> Thanks,
> 
> Shalom
> 
>  
> 
>  
> 
> Shalom Bresticker
> 
> Intel Jerusalem LAD DA
> 
> +972 2 589-6852
> 
> +972 54 721-1033 
> 
>  
> 
> 
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