Date: Mon Feb 19 2007 - 08:20:07 PST
Using Verilog-1995 port declaration syntax, we say that module m(a); input a; endmodule creates an implicit net declaration of a. Thus, if I write `default_nettype none then I get an error message that a does not have a net declaration. The same occurs if I write `default_nettype none module m(input a); though I think the LRM is a little ambiguous about that. It is common methodology to allow implicit net declarations of ports, since the name is already declared as part of a port and thus not completely undeclared, and the additional net declaration is redundant. At the same time, other implicit declarations are forbidden in many of those methodologies. The problem is that today `default_nettype does not support allowing implicit net declarations of ports while not allowing other implicit net declarations. I would like to see this added. Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
