Re: [sv-bc] When are constant expressions evaluated?

"Bresticker, Shalom" wrote:
> 
> Is there any significance to the legality of a default value
> of the parameter, or only to the actual instantiated values?

I think there was someone using Verilog-AMS who wanted to make
a parameter mandatory (ie, you must specify it) and thus gave
an illegal default.  However, in this case, he was using the
"ranges" allowed in AMS paramter declarations:

parameter real myparm = -1 from (0:inf);

where (0:inf) means that only positive values are allowed.

-Geoffrey

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