RE: [sv-bc] Is dynamic variable written in continuous assignment

From: Rich, Dave <Dave_Rich_at_.....>
Date: Thu Nov 02 2006 - 07:26:38 PST
Surya,

Those cases are both legal. The array as an aggregate is a static
variable. The LRM is currently restricting references to members of the
array in non-procedural contexts.

By the way, I have on my to-do list writing a proposal to remove that
restriction on dynamic variable members (just leaving the restriction on
automatics in place). It really should be up to the user to avoid
out-of-bounds array indexing or null class handle de-references.

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Surya Pratik Saha
> Sent: Thursday, November 02, 2006 6:56 AM
> To: sv-bc@eda-stds.org
> Subject: [sv-bc] Is dynamic variable wirtten in continuous assignment
> 
> Hi,
> 1800 LRM (section 6.6 Scope and lifetime) mentioned the following
text:
> 
> *Automatic variables and members or elements of dynamic variables
class
> properties and dynamically sized variables shall not be written with
> nonblocking, continuous, or procedural continuous assignments.
> References to automatic variables and elements or members of dynamic
> variables shall be limited to proce-dural blocks.
> 
> *So are the following cases\ valid:
> *case1*:
> module top;
> 
> int b [];
> 
> int a [];
> assign a = b;
> 
> endmodule
> 
> *case2*:
> module top;
> 
> int b [];
> 
> bottom b1(b);
> 
> endmodule
> 
> module bottom(input int a[]);
> endmodule
> 
> As per LRM, they should be invalid, but some simulators are passing.
> 
> --
> Regards
> Surya.
> 
Received on Thu Nov 2 07:26:53 2006

This archive was generated by hypermail 2.1.8 : Thu Nov 02 2006 - 07:27:00 PST