Re: [sv-bc] Emailing: VHDL udpate safeguards IP

Well, IP encryption is already in Verilog.  That was apparently the
basis for the VHDL version.

PSL assertions could have been added to SV, but another route was
taken for adding assertions, so it wouldn't make much sense now.

Packages don't need to be part of the language.  I think SV has the
mechanisms Kurt Baty would need to write fixed- and floating-point
packages if desired.

The "process(all)" construct sounds like always @* or always_comb.
Hierarchical signal references for testbenches are clearly borrowed
from Verilog.  Unary reduction operators presumably are also.  Most
of the extensions seem to be borrowed from Verilog or SV, so we are
already covered.

We don't have parameterized packages in SV, but parameterized classes
may provide most of the desired functionality.

Steven Sharp
sharp@cadence.com