Date: Tue Oct 10 2006 - 11:03:10 PDT
Mac, I wouldn't hide behind your chair! I can't see anyone lobbing too many grenades except for those who may not wish to acknowledge the obvious. As you point out, the groups are cross pollinating quite well on their own that before long they will not be to distinguishable from each other. -Dennis ________________________________ From: Michael (Mac) McNamara [mailto:mcnamara@cadence.com] Sent: Tuesday, October 10, 2006 10:53 AM To: Brophy, Dennis; Bresticker, Shalom; sv-bc@eda.org Subject: RE: [sv-bc] Emailing: VHDL update safeguards IP The title refers to an item that is indeed already a part of 1364-2005 (protected envelopes), and indeed, Thompson acknowledges that VHDL incorporated this from Cadence and 1364. I believe Shalom's point was some of the other VHDL additions mentioned in the text might be candidates for P1800, which are: VHPI (no, 1364 has had PLI(s) for years) PSL integration (maybe, however, P1800 already has SVA) Floating and fixed point arithmetic for synthesis (maybe?) Process(all) (no, we already had this in 1364-2001 - always @(*), refined further in P1800 - always_comb ) Parameterizable packages (maybe there is something there we don't have already? I suspect not.) Hierarchical signal references (no, 1364 has had this since 1995) Unconstrained arrays (don't think so, 1800 has this (I think)) Simplified conditionals (don't know - Verilog's are quite simple...) Unary reduction (no 1364-1995 had this) Overloading logic operators (Is this user overloading? If so I don't think we want this) As a editorial comment - it seems that as over the past few years we have added to Verilog features that replicate the remaining places where VHDL was stronger than Verilog (structs, strong type checking, et cetera), and now it looks like VHDL has added features that replicate places where Verilog was stronger than VHDL. Perhaps soon it will be time to consolidate the two standards into one? (OK, now I am hiding behind my chair :-) ) ________________________________ From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brophy, Dennis Sent: Tuesday, October 10, 2006 10:30 AM To: Bresticker, Shalom; sv-bc@eda.org Subject: RE: [sv-bc] Emailing: VHDL udpate safeguards IP I thought this was clause 28, "Protected envelopes" in IEEE 1364-2005. -Dennis ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Tuesday, October 10, 2006 12:24 AM To: sv-bc@server.eda.org Subject: [sv-bc] Emailing: VHDL udpate safeguards IP Any of this look like a good idea for SystemVerilog as well? Shalom ________________________________ <http://as.cmpnet.com/event.ng/Type=click&FlightID=66335&AdID=114851&Tar getID=649&Segments=823,885,1411,2722,3108,3448,3598,5064,5644,7626,8440& Targets=649,786,2625,2878,4227,6070&Values=34,46,51,63,77,82,93,100,140, 203,304,309,442,450,646,1184,1255,1388,1431,1685,1766,1785,1798,1925,194 5,2217,2299,2326,2678,2727,2895,3347,3355,4079,4080&RawValues=&Redirect= https:/www.amcc.com/MyAMCC/jsp/public/productDetail/product_detail.jsp?p roductID=PPC440EPx> <http://as.cmpnet.com/event.ng/Type=click&FlightID=66335&AdID=114851&Tar getID=649&Segments=823,885,1411,2722,3108,3448,3598,5064,5644,7626,8440& Targets=649,786,2625,2878,4227,6070&Values=34,46,51,63,77,82,93,100,140, 203,304,309,442,450,646,1184,1255,1388,1431,1685,1766,1785,1798,1925,194 5,2217,2299,2326,2678,2727,2895,3347,3355,4079,4080&RawValues=&Redirect= https:/www.amcc.com/MyAMCC/jsp/public/productDetail/product_detail.jsp?p roductID=PPC440EPx> <http://as.cmpnet.com/event.ng/Type=count&ClientType=2&AdID=114851&Fligh tID=66335&TargetID=649&Segments=823,885,1411,2722,3108,3448,3598,5064,56 44,7626,8440&Targets=649,786,2625,2878,4227,6070&Values=34,46,51,63,77,8 2,93,100,140,203,304,309,442,450,646,1184,1255,1388,1431,1685,1766,1785, 1798,1925,1945,2217,2299,2326,2678,2727,2895,3347,3355,4079,4080&RawValu es=&random=caRAwyk,bcswstixewhfr> <http://www.cmp.com/> <http://eet.com/> EE Times <http://eet.com/> : Design News <http://eet.com/news/design/> VHDL udpate safeguards IP Richard Goering <mailto:rgoering@cmp.com> (10/09/2006 9:01 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=193105394 <http://eet.com/showArticle.jhtml?articleID=193105394> SANTA CRUZ, Calif. - Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week will announce it has approved a revised version of the VHDL specification. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for intellectual-property (IP) encryption. Though VHDL had heavy backing from EDA vendors when it emerged as a standard in the late 1980s, most U.S. chip designers stayed with Verilog. Today, said Gary Smith, chief EDA analyst at Gartner Dataquest, VHDL usage is declining for high-end design. But the language remains in use at some companies in Europe and Japan, he said, and FPGA designers continue to employ it. VHDL has been part of the IEEE standards process for many years, and the most recent revision is IEEE 1076-2002. But the IEEE VHDL Analysis and Standardization Group was unable to make much progress with the language after 2002, according to Accellera chairman Shrenik Mehta, so in September 2005 it turned to Accellera for help. Accellera's VHDL technical subcommittee got to work, with support from such companies as Nokia, Rockwell, IBM, Cadence Design Systems, Mentor Graphics and Synopsys. The first part of the Accellera work, the VHDL Programming Interface (VHPI), was delivered to IEEE earlier this year. Accellera now is announcing the second part, internally called Accellera VHDL-2006 3.0. The integration of PSL is among the most important enhancements in the VHDL revision. PSL statements can now appear within VHDL, where PSL has its own object class. Alternatively, users can create PSL "design units" that separate the PSL assertions from the rest of the VHDL code, said Lance Thompson, chairman of the Accellera VHDL technical subcommittee and senior engineer for IBM's technology collaboration solutions group. IP protection is a "huge" addition to VHDL, Thompson said. "If you have a significant investment in IP, you don't want to give out source code that enables users to do whatever they want with it. On the other hand, you want to facilitate its use in simulation, so users can correctly interface to the IP." Thompson said the VHDL committee adapted an en- cryption approach that Ca- dence had developed for Verilog, adding "a mechanism for hiding pieces of the source code and encrypting it with different methods." Tool suppliers can decrypt the code so it remains hidden from the IP user. The encryption is accomplished with pragmas that indicate the area of code that needs to be encrypted. Users can specify which encryption algorithm and key to use. A "viewpoints" feature lets users see signal values during simulation, but not how those values are derived. Another feature is the addition of fixed- and floating-point packages with generics for customization. Thompson said the move responds to "a long effort on the sidelines to develop synthesizable fixed- and floating-point packages for people who develop DSPs." Accellera VHDL-2006 3.0 also adds a "process(all)" construct, which provides simplified sensitivity lists. That's a big help in maintaining equivalence between synthesis and simulation, so that VHDL processes aren't synthesized one way and simulated another, Thompson said. Other enhancements include parameterizable packages using generics; hierarchical signal references for testbenches; composite types that permit elements to be unconstrained arrays; simplified conditionals; unary reduction operators; overloading of logic operators; and some 50 corrections and clarifications to the previous revision of the language. The revised VHDL standard is available to Accellera members at www. accellera.org. IEEE has Accellera's recommended improvements, Thompson said, but Accellera is recommending a period of trial implementation by vendors before IEEE completes standardization. Meanwhile, Accellera is "starting to work on object-oriented aspects for VHDL, largely as an underpinning to support transaction-level modeling," Thompson said. "It looks like we'll be able to use the underlying mechanism to support interfaces for design units and constrained-random simulation environments. And we're open to ideas." All material on this site Copyright (c) 2006 CMP Media LLC <http://www.cmp.com/delivery/copyright.html> . All rights reserved. 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