Re: [sv-bc] assignment to input

Michael (Mac) McNamara wrote:
[...]
> I personally like the ability to read from outputs, and find other
> languages that forbid this to be not helpful.  The one clear case where
> reading from an output is quite useful is in a $display or $monitor of
> the signals in a module.

As a side note, my understanding is that VHDL 200x will permit
one to read an output so we might not want to "regress" to
old VHDL semantics.... :-)

Gord.
-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com