[sv-bc] Name resolution sub-group

A few meetings ago, SV-BC decided to set up a group to
determine name resolution rules for SystemVerilog.  Right
now we have the following people in the group:
     Gord Vreugdenhil          (Mentor)
     Francoise Martinolle      (Cadence)
     Steven Sharp              (Cadence)
     Mark Hartoog              (Synopsys)
     Shalom Bresticker         (Intel)

If you are interested in participating or being cc'd on the
detailed discussions, please let me know.  The group will
of course keep EC and BC informed as consensus on major
issues is reached or if serious disagreement arises that
needs wider discussion.

Gord.
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com