[sv-bc] Mixing of ANSI style and V995 ports in a single module

It appears that several implementations are supporting the following
style of port declarations based on user requests.

 

 

module test (output A, input B, C);

    reg A;

    wire B, C;

 

    always @*

        A = B & C;

 

endmodule

 

This comes from putting parentheses around the V1995 style input/output
statements . I can understand someone wanting to do this when moving
from V1995 to V2001, but I'm wondering if this would cause a problem in
SystemVerilog.

 

Dave

 

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625