Re: [sv-bc] Re: Sysfunc to ask about signedness?

>     `define IS_SIGNED(x) &(((((x) << $bits(x)) + 1'sb1) <<
>($bits(x)-1)) >>> $bits(x))


A simpler variation that should work also:

	`define IS_SIGNED(x) &(((x) | ~1'sb0) >>> $bits(x))

An even simpler version that should work in Verilog too:

	`define IS_SIGNED(x) (((x) | ~0) < 0)

Steven Sharp
sharp@cadence.com