[sv-bc] Re: Sysfunc to ask about signedness?

Following up on http://eda-stds.org/svdb/bug_view_page.php?bug_id=1479
<http://eda-stds.org/svdb/bug_view_page.php?bug_id=1479>  , here's a
run-time check for signedness that's backward compatible with any
version of SystemVerilog --
 
     `define IS_SIGNED(x) &(((((x) << $bits(x)) + 1'sb1) <<
($bits(x)-1)) >>> $bits(x))
 
-- Brad

________________________________

From: Brad Pierce 
Sent: Tuesday, February 07, 2006 9:45 AM
To: 'sv-bc@eda.org'
Subject: Sysfunc to ask about signedness?



Should there be a standard system function to ask during conditional
generate whether a type parameter (for example) is signed?  It's not
strictly necessary, because a simple macro will do the job -

 

     `define IS_SIGNED(x) (type(x)'('1) < type(x)'('0))

 

but it's still surprising that there's no standard system function for
this.

 

-- Brad