RE: [sv-bc] implicit declarations in port expressions

It seems that .a(b) is more a 12.3.2 (or 12.3.1) syntax. 12.3.3 only
gives an example of such syntax. So, just to be sure I understand you
right, my understanding is that the identifier "b" in all 3 following
examples should be considered an implicit declaration:

 

module m1(b);

input b;

endmodule

 

module m2(.a(b));

input b;

endmodule

 

module m3(input b);

endmodule

 

If this is correct, then there is a need to find a phrasing that will
unambiguously cover all three.

 

--Yulik.

 

________________________________

From: Bresticker, Shalom 
Sent: Monday, June 12, 2006 4:26 PM
To: Feldman, Yulik; 'sv-bc@server.verilog.org'
Subject: RE: [sv-bc] implicit declarations in port expressions

 

That is what I wrote. It should refer to 12.3.4 also, in my opinion.

However, the .a(b) is 12.3.3 syntax and requires a port declaration for
b.

 

Shalom

 

________________________________

From: Feldman, Yulik 
Sent: Monday, June 12, 2006 4:21 PM
To: Bresticker, Shalom; 'sv-bc@server.verilog.org'
Subject: RE: [sv-bc] implicit declarations in port expressions

 

I'm OK with that interpretation, if you say it is the intention.
However, I'm still unclear about the port_identifiers in list_of_ports (
"b" in "module m(.a(b));"). Does 4.5 refer to port_identifiers in
list_of_port_declarations only, or to port_identifiers in lira_of_ports
as well? Shouldn't it refer to both for consistency?

 

________________________________

From: Bresticker, Shalom 
Sent: Monday, June 12, 2006 3:58 PM
To: Feldman, Yulik; sv-bc@server.verilog.org
Subject: RE: [sv-bc] implicit declarations in port expressions

 

I would have said the following:

 

You are correct that every port identifier in the list of ports for the
module declaration has to have a corresponding port declaration (input,
output, or inout). The port declaration may omit declaring the
variable/net type of the port. In that case, the net/variable may be
declared separately. If not, it is implicitly declared as a net of
default net type, with the characteristics (attributes) appearing in the
port declaration. And that is what 4.5 is referring to.

 

I would have said that, meaning that the "port expression declaration"
phrase appearing in 4.5 is referring to the input/output/inout
declaration. The proof is that 4.5 also refers to the "vector width of
the port expression declaration", which does not appear in the list of
ports for the module declaration.

 

Yes, I would have said that, and I still think that is what was
intended. Having said that, I now see some problems in the wording:

 

4.5 refers to a "port expression declaration", whereas these are not
"port expression declarations", but rather "port declarations" or maybe
"port identifier declarations". No expression is being declared.

 

Since the port declarations may appear in the module header in "ANSI C"
style, the statement is equally applicable there, so 4.5 should refer to
12.3.4 as well as 12.3.3.

 

And 12.3.3 and 12.3.4 should also say that if the net/variable type is
not declared in the port declaration, nor separately (in the case of
12.3.3), then a net is implicitly declared.

 

Shalom

 

________________________________

From: owner-sv-bc@server.verilog.org
[mailto:owner-sv-bc@server.verilog.org] On Behalf Of Feldman, Yulik
Sent: Monday, June 12, 2006 3:14 PM
To: sv-bc@server.verilog.org
Subject: [sv-bc] implicit declarations in port expressions

 

Hi,

 

1364-2005 section 4.5 "Implicit declarations" says: 

 

"If an identifier is used in a port expression declaration, then an
implicit net of default net type shall be assumed, with the vector width
of the port expression declaration. See 12.3.3 for a discussion of port
expression declarations".

 

However, the term "port expression declaration" is not defined and is
not referenced anywhere except the above paragraph. Was the intention to
write "port expression in a port declaration", to refer to identifiers
like the identifier "b" in "module m(.a(b));"?

 

If the answer is "yes", then there is also a semantics question with
regard to that paragraph. Consider that we have an implicit declaration
"b" like in the example above. However, section 12.3.3 "Port
declarations" says: 

 

"Each port_identifier in a port_expression in the list of ports for the
module declaration shall also be declared in the body of the module as
one of the following port declarations: input, output, or inout
(bidirectional)".

 

Which means that if the direction is not declared in the body of the
module, such an implicit declaration is an error anyway. And if the
direction is declared, should the identifier indeed be treated as an
implicit declaration? So, what is the intention of the text in section
4.5 and what is the expected semantics?

 

Thanks,

            Yulik.