[sv-bc] implicit declarations in port expressions

Hi,

 

1364-2005 section 4.5 "Implicit declarations" says: 

 

"If an identifier is used in a port expression declaration, then an
implicit net of default net type shall be assumed, with the vector width
of the port expression declaration. See 12.3.3 for a discussion of port
expression declarations".

 

However, the term "port expression declaration" is not defined and is
not referenced anywhere except the above paragraph. Was the intention to
write "port expression in a port declaration", to refer to identifiers
like the identifier "b" in "module m(.a(b));"?

 

If the answer is "yes", then there is also a semantics question with
regard to that paragraph. Consider that we have an implicit declaration
"b" like in the example above. However, section 12.3.3 "Port
declarations" says: 

 

"Each port_identifier in a port_expression in the list of ports for the
module declaration shall also be declared in the body of the module as
one of the following port declarations: input, output, or inout
(bidirectional)".

 

Which means that if the direction is not declared in the body of the
module, such an implicit declaration is an error anyway. And if the
direction is declared, should the identifier indeed be treated as an
implicit declaration? So, what is the intention of the text in section
4.5 and what is the expected semantics?

 

Thanks,

            Yulik.