RE: [sv-bc] Is #4.2step legal?

Can someone *please* explain what on earth they think
#Nstep is for, given N>1 ?  I am completely at a loss
to imagine any situation in which it is either robust 
or useful.

I am also mystified by any attempt to give meaning 
to fractional steps.

It seems to me that the LRM would be wise to treat #1step
as a special case in which the number can only be 1.
-- 
Jonathan Bromley, Consultant

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> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]On
> Behalf Of Rich, Dave
> Sent: 19 May 2006 06:12
> To: Steven Sharp; sv-bc@server.eda.org; stuart@sutherland-hdl.com;
> Arturo.Salz@synopsys.com
> Subject: RE: [sv-bc] Is #4.2step legal?
> 
> 
> Steven is right; this is a huge oversight in the LRM. Section 
> 3.5 needs
> to define the semantics of the 'step' delay as ignoring all local
> timescales and precisions and needs to be defined to be the scaled to
> the smallest global precision.
> 
> Dave
> 
> 
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On
> > Behalf Of Steven Sharp
> > Sent: Thursday, May 18, 2006 4:39 PM
> > To: sharp@cadence.com; sv-bc@server.eda.org;
> stuart@sutherland-hdl.com;
> > Arturo.Salz@synopsys.com
> > Subject: RE: [sv-bc] Is #4.2step legal?
> > 
> > 
> > >From: "Arturo Salz" <Arturo.Salz@synopsys.com>
> > 
> > >Unfortunately, defining "step" as anything other than the 
> global time
> > >precision would render the step unit largely useless for 
> the purpose
> for
> > >which it was conceived: To allow users to specify the 
> smallest delay
> > >possible such that no events can take place at a time in between T
> and T
> > >+ 1step. This is useful for specifying the sampling skew 
> of clocking
> > >blocks.
> > 
> > For this to work, sampling skews would have to ignore the 
> normal time
> > precision rules that apply to all other delays in Verilog 
> (e.g. delay
> > controls, continuous assignment and gate delays).  I don't see
> anything
> > in the LRM that says that they do.
> > 
> > If you used #4.2step as a delay control in a module whose time
> precision
> > was higher than the global time precision, this would get 
> rounded down
> > to zero.  For example, if the global time precision is 1fs, and the
> local
> > time precision and time unit are 1ps, then #4.2step would be
> equivalent
> > to #0.0042, which would be rounded to zero.  You cannot specify a
> delay
> > in the module with more precision than the module time precision.
> That
> > is what the time precision means.
> > 
> > Steven Sharp
> > sharp@cadence.com
> 
> 
>