RE: [sv-bc] systemverilog-users mailing list?

From: Rich, Dave <Dave_Rich_at_.....>
Date: Thu May 18 2006 - 10:38:36 PDT
Edmond,

You're right this is a relatively small group of people, and we are mainly here to clarify and interpret the language. And this is the forum to present enhancements or problems with the spec. 

You might try one of the Yahoo groups like ASICDESIGN which has over 4000 subscribers. There are a few SystemVerilog-only groups, but none of them have much activity yet. I was surprised to find that there are over 70 different groups that have Verilog in their description.

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
> Behalf Of Edmond Coté
> Sent: Thursday, May 18, 2006 7:38 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] systemverilog-users mailing list?
> 
> Hi,
> 
> I subscribed to this mailing list with hopes of connecting with other
> SystemVerilog users and from the looks of it, this is not the right
> place.
> 
> Any suggestions? More specifically, I'm playing around with the
> synthesizable portion of the language (or lack thereof).
> 
> Thanks,
> 
> --
> Edmond Cote
> Research Assistant
> Queen's University - Computer Architecture Lab
Received on Thu May 18 10:38:28 2006

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