Re: [sv-bc] systemverilog-users mailing list?

We can touch upon an aspect that was not so directly dealt with so
far. We ultimately aim to serve the basic purpose of design and
verification.

-- Joginder

On 5/18/06, Brad Pierce <Brad.Pierce@synopsys.com> wrote:
> Edmond,
>
> Among the 150+ sv-bc subscribers, including among its most active participants, are a lot of early-adopting users.
>
> Why not start a conversation here about what's on your mind regarding SystemVerilog design and see what happens?
>
> -- Brad
>
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Edmond Coté
> Sent: Thursday, May 18, 2006 7:38 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] systemverilog-users mailing list?
>
> Hi,
>
> I subscribed to this mailing list with hopes of connecting with other
> SystemVerilog users and from the looks of it, this is not the right
> place.
>
> Any suggestions? More specifically, I'm playing around with the
> synthesizable portion of the language (or lack thereof).
>
> Thanks,
>
> --
> Edmond Cote
> Research Assistant
> Queen's University - Computer Architecture Lab
>
>
>