RE: [sv-bc] 10.8 Named blocks and statement labels - question

Follow-up question:

10.9 has the following example, 

module ...
always always1: begin ... t1: task1( ); ... end
...
endmodule
always begin
...
disable u1.always1.t1; // exit task1, which was called from always1
(static)
end

(Here also the IEEE reformatting caused "(static)" to jump to the next
line.)

The question is, the statement label 'always1' here is used as a
hierarchical scope, where 10.8 does not say that labels create such
scopes.

I found that
17.2 ("Immediate assertions") says, "The optional statement label
(identifier and colon) creates a named block around the assertion
statement (or any other SystemVerilog statement) and can be displayed
using the %m format specification."

Such a statement certainly belongs in 10.8 and also in the discussion of
hierarchies in Clause 19.

Shalom


> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Bresticker, Shalom
> Sent: Thursday, February 09, 2006 1:11 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] 10.8 Named blocks and statement labels -
> question
> 
> 10.8 has the following example:
> 
> labelB: fork // label before the begin or fork
> ...
> join : labelB
> 
> 
> The block_identifier labelB after 'join' is not clear. This is
> a block_identifier whereas the labelB before the 'fork' is a
> statement label, not a block identifier.
> 
> Thanks,
> Shalom
> 
> 
> Shalom Bresticker
> Intel Jerusalem LAD DA
> +972 2 589-6852
> +972 54 721-1033
> I don't represent Intel