RE: [sv-bc] compiler directives in middle of statement

But can `pragma protect occur in the middle of a statement?
Does the LRM forbid it?

Shalom

> -----Original Message-----
> From: Michael (Mac) McNamara [mailto:mcnamara@cadence.com]
> Sent: Wednesday, January 04, 2006 6:30 PM
> To: Bresticker, Shalom; Steven Sharp; sv-bc@eda.org
> Subject: RE: [sv-bc] compiler directives in middle of statement
> 
> It is very useful to allow judicious placement of the `pragma
> protect to
> enable hiding of the contents of a module without hiding the
> whole
> thing, for example:
> 
> module foo ( output o; input a,b );
> 
> `pragma protect
> always @( a or b) begin
>   // some funky proprietary function of a & b and the phase of
> the moon
> to calculate o
> end
> `pragma endprotect
> 
> endmodule.
> 
> The above module (once encrypted) can be use in a hierarchy by
> coverage
> tools, lint tools, et cetera, which will
> properly hook up everything, but will not know the innards of
> the
> protected region.  Hence the proprietary secrets are kept
> secret, while
> the user of these support tools doesn't get 'missing definition
> of
> moudle foo' type errors.  An attempt to simulate the design
> will fail,
> however.
> 
> The library vendor could go so far as to provide:
> 
> module foo ( output o; input a,b );
> 
> parameter dly = 1;
> `pragma protect
> defparam dly 0.9367
> `prgama enprotect
> 
>   always @( a or b) begin
>     o <= (#dly) a ^ b;
>   end
> 
> endmodule.
> 
> so that simulation without the proper decode key gets generic
> results,
> but with the proper key gets the super secret actual delay.
> (this also
> shows a valid use of defparam, B.T.W.)
> 
> 
> Michael McNamara
> mcnamara@cadence.com
> 408-914-6808 work
> 408-348-7025 cell
> 
> 
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of
> Bresticker, Shalom
> Sent: Wednesday, January 04, 2006 4:20 AM
> To: Steven Sharp; sv-bc@eda.org
> Subject: RE: [sv-bc] compiler directives in middle of statement
> 
> The following are 'interesting' cases:
> 
> - sv, unlike Verilog, allows all sorts of code outside modules.
> 
> - The following directives don't say they are restricted to
> being
> outside modules: `celldefine, `timescale
> 
> - `pragma
> 
> - `pragma protect
> 
> 
> Shalom
> 
> 
> > -----Original Message-----
> > From: Steven Sharp [mailto:sharp@cadence.com]
> > Sent: Wednesday, January 04, 2006 2:16 AM
> > To: sv-bc@eda.org; Bresticker, Shalom
> > Subject: Re: [sv-bc] compiler directives in middle of
> statement
> >
> > The LRM restricts some compiler directives to specific
> places,
> > such as
> > outside of modules (generally because they are intended to
> > apply to an
> > entire module, and it would be confusing if they changed in
> the
> > middle
> > of the module).  Aside from those, I think compiler
> directives
> > are
> > allowed anywhere you like, including in the middle of
> > statements.
> >
> > The simulators I have access to have no problem with a macro
> > definition
> > in the middle of a continuous assignment.
> >
> > Steven Sharp
> > sharp@cadence.com