RE: [sv-bc] compiler directives in middle of statement

Well, then that answers your original question. There is nothing that
restricts compiler directive use in the middle of a statement, so it is
legal.

Dave


> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
> Sent: Wednesday, January 04, 2006 12:22 PM
> To: Rich, Dave; sv-bc@eda.org
> Subject: RE: [sv-bc] compiler directives in middle of statement
> 
> Dave,
> 
> 1364-2005, 19.3.1, says, "The text specified for macro text shall not
be
> split across the following lexical tokens:
> - Comments
> - Numbers
> - Strings
> - Identifiers
> - Keywords
> - Operators"
> 
> Shalom
> 
> > -----Original Message-----
> > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> > Behalf Of Rich, Dave
> > Sent: Wednesday, January 04, 2006 8:27 PM
> > To: sv-bc@eda.org
> > Subject: RE: [sv-bc] compiler directives in middle of statement
> >
> > I think the description for how compiler directives are
> > processed is
> > missing from the LRM. Specifically in the case of `define,
> > there is
> > nothing in the 1364 description that would prevent
> >
> > `define M module
> > `M m;
> > end`M
> >
> > But somehow, we all seem to know that the backtick(`)
> > introduces
> > whitespace even after the text substitution. We've all assumed
> > that the
> > compiler directives are parsed along with the source
> > descriptions, so
> > 'end' is recognized as a keyword token before `M is expanded
> > into the
> > source description.
> >
> > Of the other compiler directives allowed outside a module
> > definition, I
> > don't know of any issues with the limited set of SystemVerilog
> > constructs that are also allowed outside a module definition.
> >
> > Dave
> >
> >
> >
> >
> > > -----Original Message-----
> > > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> > Behalf Of
> > > Bresticker, Shalom
> > > Sent: Wednesday, January 04, 2006 4:20 AM
> > > To: Steven Sharp; sv-bc@eda.org
> > > Subject: RE: [sv-bc] compiler directives in middle of
> > statement
> > >
> > > The following are 'interesting' cases:
> > >
> > > - sv, unlike Verilog, allows all sorts of code outside
> > modules.
> > >
> > > - The following directives don't say they are restricted to
> > being
> > > outside modules: `celldefine, `timescale
> > >
> > > - `pragma
> > >
> > > - `pragma protect
> > >
> > >
> > > Shalom
> > >
> > >
> > > > -----Original Message-----
> > > > From: Steven Sharp [mailto:sharp@cadence.com]
> > > > Sent: Wednesday, January 04, 2006 2:16 AM
> > > > To: sv-bc@eda.org; Bresticker, Shalom
> > > > Subject: Re: [sv-bc] compiler directives in middle of
> > statement
> > > >
> > > > The LRM restricts some compiler directives to specific
> > places,
> > > > such as
> > > > outside of modules (generally because they are intended to
> > > > apply to an
> > > > entire module, and it would be confusing if they changed in
> > the
> > > > middle
> > > > of the module).  Aside from those, I think compiler
> > directives
> > > > are
> > > > allowed anywhere you like, including in the middle of
> > > > statements.
> > > >
> > > > The simulators I have access to have no problem with a
> > macro
> > > > definition
> > > > in the middle of a continuous assignment.
> > > >
> > > > Steven Sharp
> > > > sharp@cadence.com