[sv-bc] why is it ILLEGAL ?

From: Nasim Hussain <Nasim.Hussain_at_.....>
Date: Sun Dec 18 2005 - 11:43:54 PST
hi-

i had a small question, it is more related to verilog data types, but
thought i would ask it here anyway, since i have a feeling it will also
apply to SV data types.


this is with regards to the following line
	(taken from IEEE Std. 1364-2001)


section 3.2.1 and 3.2.2 under chapter 3 ("data types") both say:

	"it is illegal to redeclare a name already declared by a net,
parameter, or variable declaration"


i am failing to understand why it is ILLEGAL ? for example, i don't see
anything wrong with the following:


	module top();
	wire x;
	...
	wire x;
		cpu U1 (.a(x) ...)
		mcu U2 (.b(x) ...)
	endmodule


yes, wire x is declared twice, but it is of the SAME data type. i don't
think this should even be a warning, forget an error! anyhow, one
simulator says it is a warning during compilation (OK, i accepted that,
but with reservations), whereas another one (well 2 of them actually)
straight said "no sir, that is an error!", and quits.

it isn't like i have "wire x;" and then "reg x;"... which, despite it's
being redeclared, IMO should be inferred from the logic it is being used
to construct. for example-

	wire x;
	reg x;
	always @(posedge clk)
		q <= d;

it is obvious here that the user intends to create a +ve-edge-triggered
FF... meaning the compiler SHOULD accept it rightfully as a reg (i am
not saying "assign x = ", in which case yes, the compiler should flag it
as an error!).

then again, under section 12.6 (scope rules), i see in the very 1st
paragraph - "an identifier shall be used to declare only one item within
a scope. this rule means it is ILLEGAL to declare two or more variables
that have the SAME name... "

come on... are they being serious here ? :D

will someone kindly tell me what is wrong with the following:

	module top();
	reg a;
	reg a;
	reg a;
	reg a;
	reg a;
	endmodule

-nasim

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Received on Sun Dec 18 11:43:59 2005

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