>Subject: [sv-bc] 6.3.5 Hierarchical references in parameter assignments >From: "Bresticker, Shalom" <shalom.bresticker@intel.com> > >6.3.5 says, >"A value parameter (parameter, localparam or specparam) can only be set to an expression of literals, value parameters or local parameters, genvars, enumerated names, or a constant function of these. Package references are allowed. Hierarchical names are not allowed." > >In 1364 ETF issue #272 (http://boyd.com/1364_btf/report/full_pr/272.html), the following came up: > >">What is the motivation for requiring constant expressions in defparams >>and parameter declarations, but not in the parameter value assignments >>in module instantiations? That is, in A.4.1, why don't >>ordered_parameter_assignment and named_parameter_assignment require >>constant_expression? > >These certainly have to be constant expressions. I'm not sure whether >they have to conform to the same restrictions as defparams, though. >For example, Verilog-XL appears to allow hierarchical names in module instantations >but not in defparams." > >So I am not sure about the statement, "Hierarchical names are not allowed." > >Comments? Yes, XL does appear to allow hierarchical names in this case, and some other simulators have followed suit to maintain compatibility with XL. I don't know whether this was a deliberate decision in XL, or an accidental hole in the checking. It certainly seems inconsistent. Steven Sharp sharp@cadence.comReceived on Mon Nov 28 11:10:36 2005
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