RE: [sv-bc] 6.3.5 Hierarchical references in parameter assignments

The rule in the standard may have been part of the general disregard for
defparams (make them less flexible, and people won't use them); more
likely the technical reason for the restriction on defparam value
assignment was the tight embrace of defparam processing with design
elaboration made for a chicken & egg problem that one needed to evaluate
defparams first as they could influence elaboration, and hence could not
process a hierarchal reference to determine a defparam value as
elaboration hadn't been done yet...

Defparams could also just have been implemented that way in XL because
that was good enough for the modeling problem that needed to be solved.
Evolutionary design does end up with things like appendixes and the
like.


Michael McNamara
mcnamara@cadence.com
408-914-6808 work
408-348-7025 cell


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Monday, November 28, 2005 11:10 AM
To: sv-bc@eda.org; shalom.bresticker@intel.com
Subject: Re: [sv-bc] 6.3.5 Hierarchical references in parameter
assignments


>Subject: [sv-bc] 6.3.5 Hierarchical references in parameter assignments
>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>
>6.3.5 says,
>"A value parameter (parameter, localparam or specparam) can only be set
to an 
expression of literals, value parameters or local parameters, genvars, 
enumerated names, or a constant function of these. Package references
are 
allowed. Hierarchical names are not allowed."
>
>In 1364 ETF issue #272
(http://boyd.com/1364_btf/report/full_pr/272.html), the 
following came up:
>
>">What is the motivation for requiring constant expressions in
defparams 
>>and parameter declarations, but not in the parameter value assignments

>>in module instantiations? That is, in A.4.1, why don't 
>>ordered_parameter_assignment and named_parameter_assignment require 
>>constant_expression? 
>
>These certainly have to be constant expressions. I'm not sure whether 
>they have to conform to the same restrictions as defparams, though. 
>For example, Verilog-XL appears to allow hierarchical names in module 
instantations 
>but not in defparams."
>
>So I am not sure about the statement, "Hierarchical names are not
allowed."
>
>Comments?

Yes, XL does appear to allow hierarchical names in this case, and some
other simulators have followed suit to maintain compatibility with XL.

I don't know whether this was a deliberate decision in XL, or an
accidental hole in the checking.  It certainly seems inconsistent.

Steven Sharp
sharp@cadence.com