[sv-bc] ref variable initialization

Hi,
If a ref variable initialized at the time of declaration, will it be treated as
procedural assignment?
Also if the variable passed in ref argument, will it take as an assignment to
that value, if ref is initialized?

As per SV LRM,
5.4 Variables
                   A variable declaration consists of a data type followed by
one or more instances.
                   shortint s1, s2[0:9];
                   A variable can be declared with an initializer, for example:
                   int i = 0;
                   In Verilog-2001, an initialization value specified as part of
the declaration is
                   executed as if the assignment were made from an initial
block, after simulation
                   has started.
                   Therefore, the initialization can cause an event on that
variable at simulation
                   time zero.
                   In SystemVerilog, setting the initial value of a static
variable as part of the
                   variable declaration (including static class members) shall
occur before any
                   initial or always blocks are started, and so does not
generate an event. If an
                   event is needed, an initial block should be used to assign
the initial values.

But nothing specified for ref variable.

What will be the behaviour for the following test case?
module xx;
     function int f(ref int x = 1);
        return x;
     endfunction
     int y, z;
    initial begin
        z = f(y);
        #5 $display ("y = %b", y);
    end
    always_comb
        f.x = 1;

endmodule

Will y give 1 or x?
Also as per LRM, for always_comb
The variables written on the left-hand side of assignments shall not be written
to by any other process.

So for f.x assignment, is it an error case?

Regards
Surya.