RE: [sv-bc] Package Questions

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Fri Aug 12 2005 - 06:52:56 PDT
Just my $0.02:

> (1) Can one declare extern task and extern functions in a 
> package? A tried
> to follow the BNF for the answer and I think I found a BNF-thread that
> wound its way through some type of class-item to make this legal, but
> thought I would ask the group.

Don't know - interesting question.
 
> (2) Can a package with useful typedefs be wildcard-imported (or even
> specific pkg::typedef imported) before it is needed for 
> ANSI-style ports?

For sure: just put the import statement at the top level of the file, 
so that it's imported into the compilation unit scope.  This provides
a really clean way of applying a bunch of declarations to more than
one compile - far better than requiring that the compilation-unit
scope span more than one file.  Each file has its own imports,
and stands alone.

> Do I have to use Verilog-1995 style ports in order to get a package
> imported before the typedefs are referenced?

No; I use file-level imports extensively for exactly this.
Must be my inner VHDL-programmer leaking out :-)
 
> (3) Is the group of the general opinion that we are moving away from
> $root/$unit global typedefs and task/function declarations in favor of
> packaged and imported copis of the same? (Methodology-opinion 
> question)

Again, just my opinion: if something's worth declaring at the file 
level, it's interesting to more than one module and therefore it's 
worth putting into a package.  So, although I have no idea what the
"general opinion" is, I would surely lean towards using packages
wherever it makes sense.

Of course, if you import a package (or any definition) into 
the compilation unit scope, that's tantamount to declaring it 
right there at the compilation-unit level.  But you centralise
the declaration(s) in the package, which has to be a good thing.

-- 
Jonathan Bromley, Consultant

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Received on Fri Aug 12 06:53:06 2005

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