Re: [sv-bc] Naming of unnamed sequential blocks

I agree with Steven Sharp. My personal opinion is that declarations
should not be allowed in unnamed blocks. And, if declarations are
allowed, the LRM should specify a naming convention that is consistent
across the whole language.

Inconsistent naming has (and still is) been big problem here when a
user runs equivalence check on the synthesis output and it fails due
to a name mismatch.

- Krishna.


Steven Sharp wrote:
> Mark Hartoog wrote:
> 
>>The hierarchical name 't.blk.y' is perfectly valid. Now if I modify this 
>>design to System Verilog and add a variable in the enclosing unnamed block:
>>
>>module test;
>>task t;
>>input x;
>>begin
>>   reg z;
>>   if (x) begin : blk
>>       reg y;
>>   end
>>end
>>endtask
>>initial $display(t.blk.y);
>>endmodule
>>
>>Is the hierarchical name 't.blk.y' now illegal?
> 
> 
> In my opinion, yes.
> 
> Declaring reg z is short-hand for naming the block and then
> declaring reg z inside it.  You save the effort of naming
> the block yourself, but give up the ability to refer to the
> name.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
> 


-- 
Krishna
408-215-6152