Steven Sharp wrote: > Mark Hartoog wrote: > >>The hierarchical name 't.blk.y' is perfectly valid. Now if I modify this >>design to System Verilog and add a variable in the enclosing unnamed block: >> >>module test; >>task t; >>input x; >>begin >> reg z; >> if (x) begin : blk >> reg y; >> end >>end >>endtask >>initial $display(t.blk.y); >>endmodule >> >>Is the hierarchical name 't.blk.y' now illegal? > > > In my opinion, yes. > > Declaring reg z is short-hand for naming the block and then > declaring reg z inside it. You save the effort of naming > the block yourself, but give up the ability to refer to the > name. I agree with Steven's interpretation on this. This is a case of not being able to have your cake and eat it too. You either need to name the block or you don't get visibility from the source. Gord. > Steven Sharp > sharp@cadence.com > -- -------------------------------------------------------------------- Gordon Vreugdenhil, Staff Engineer 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.comReceived on Thu May 19 13:05:36 2005
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