Re: [sv-bc] Keywords

Randy Misustin wrote:
>
> Clifford E. Cummings wrote:
> 
> > The top-level config recognition that Kev proposed would require 
> > simple changes by implementation "N" and implementation "M" and the 
> > changes seem to be small and reasonable.
> >
> > One implementation would now allow "config" to be used within the 
> > boundaries of module-endmodule, macromodule-endmodule and 
> > primitive-endprimitive.
> >
> > The other implementation would now read top-level config-endconfig 
> > without the use of a command line switch.
> >
> > Seems like relatively simple concessions on the part of both 
> > implementations (spoken by someone who has never implemented a Verilog 
> > tool!) 
> 
> Unfortunately, SystemVerilog allows variable declarations in the same 
> outer [$unit] scope as config's appear and variable declarations can 
> begin with an identifier. You'd have to get into the ugly space of only 
> allowing 'config' for non-type identifiers or significantly limit the 
> parsing technology that would be capable of recognizing the language 
> (neither choice is very appealing).
>

That is correct. However, in order to create a conflict at that level, users would
first have to create a user-defined type named "config" and then instantiate a
a variable of that type in the $unit scope. Do not intrepret this as an opinion on
this debate: I can completely see both sides of this argument.

    Arturo 
 
> -randy
>