Re: [sv-bc] FW: interpretation of priority if-else or case statement

From: Clifford E. Cummings <cliffc_at_.....>
Date: Wed Mar 30 2005 - 14:49:03 PST
Hi, Brad -

I actually use the example you have shown below (assign all 0's and then 
conditionally update the enabled output).

Over the years, Synopsys tools have sometimes optimized this version better 
than the one I sent in the previous email message and at other times the 
other version has optimized better than this version (really messes up my 
notes when we go through the lab reviews the following day   ;-)

This version works well if you are driving a vector and can pick off the 
individual bits of the vector as an index (as shown), while the other 
version works well when the decoded signals have different variable names 
(then of course the initial default assignment is either a set of 
assignments to all the variables, or a concatenation of the output 
variables assigned to all 0's).

At 02:29 PM 3/30/2005, you wrote:
>Cliff,
>
>Why would we want a case for this example?  Why not just --
>
>    module decode4
>    (output reg [3:0] y,
>     input      [1:0] a,
>     input            en);
>
>    always_comb begin
>      y = '0;
>      y[a] = en ? '1 : '0;
>    end
>
>    endmodule
>
>or

I tend to avoid generates unless I really need them. I have a cautionary 
guideline to avoid for-loops in RTL code as they can infer some very 
unexpected and inefficient logic when synthesized (I have examples in my 
Advanced Verilog class labs that really blow people away).

>   // Using new generate
>   module decode4
>    (output reg [3:0] y,
>     input      [1:0] a,
>     input            en);
>
>   for (genvar I = 3; I >= 0; I--) begin
>     assign y[I] = (a == I) ? en : '0 ;
>   end
>
>   endmodule
>
>or
>
>   //Using old generate
>   module decode4
>    (output reg [3:0] y,
>     input      [1:0] a,
>     input            en);
>
>   genvar I;
>
>   generate for (I = 3; I >= 0; I--) begin:GEN
>     assign y[I] = (a == I) ? en : '0 ;
>   end endgenerate
>
>   endmodule
>
>-- Brad

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Wed Mar 30 14:53:15 2005

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