Re: [sv-bc] FW: Multiple implicit nets in single continuous assignment

I looked at what implementations actually do.

I checked two simulators in v2k1 mode, changing the '1 to 1.

Both passed compilation.

Shalom


"Maidment, Matthew R" wrote:

> >-----Original Message-----
> >Date: Tue, 29 Mar 2005 18:13:13 +0530
> >From: "Rohit K. Jain" <rohit_jain@mentorg.com>
> >To: sv-bc@server.eda.org
> >Subject: Multiple implicit nets in single continuous assignment
> >
> >Is the case below a legal case?
> >
> >Verilog LRM 3.5 says
> >=======
> >If an identifier appears on the left-hand side of a continuous
> >assignment statement,and that identifier has not been declared
> >previously,an implicit scalar net declaration of the default
> >net type is
> >assumed.
> >=======
> >
> >Does it imply that in case of implicit net, LHS of continuous
> >assignment
> >can have only simple identifier expression?
> >Can more than one implicit nets be created in a single continuous
> >assignment, as is the case below?
> >
> >
> >module top();
> >        assign {a,c} = '1;
> >endmodule
> >
> >
> >Regards
> >Rohit
> >
> >

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