Re: [sv-bc] FW: Multiple implicit nets in single continuous assignment

Hi, Rohit -

I added this to the Verilog-2001 standard to close the loophole in the 
Verilog-1995 standard that allowed the implicit creation of all 1-bit nets 
without declaration. In Verilog-1995, all 1-bits nets were implicitly 
declared EXCEPT if the 1-bit net did was on the LHS of a continuous 
assignment and that net did not go to a port. This was most annoying to 
have such a silly exception. The 3.5 wording was intended to close that 
loophole.

So although it may not be entirely clear from the LRM wording, your example 
should indeed infer implicit declarations for both of the concatenated 
1-bit nets. If you want to file an issue regarding the wording to have the 
wording clarified, I would have no problem with that. I would ask that you 
submit first-cut clarification-wording that you believe would clarify this 
point.

Hope this helps.

Regards - Cliff

At 07:23 AM 3/29/2005, Maidment, Matthew R wrote:
> >-----Original Message-----
> >Date: Tue, 29 Mar 2005 18:13:13 +0530
> >From: "Rohit K. Jain" <rohit_jain@mentorg.com>
> >To: sv-bc@server.eda.org
> >Subject: Multiple implicit nets in single continuous assignment
> >
> >Is the case below a legal case?
> >
> >Verilog LRM 3.5 says
> >=======
> >If an identifier appears on the left-hand side of a continuous
> >assignment statement,and that identifier has not been declared
> >previously,an implicit scalar net declaration of the default
> >net type is
> >assumed.
> >=======
> >
> >Does it imply that in case of implicit net, LHS of continuous
> >assignment
> >can have only simple identifier expression?
> >Can more than one implicit nets be created in a single continuous
> >assignment, as is the case below?
> >
> >
> >module top();
> >        assign {a,c} = '1;
> >endmodule
> >
> >
> >Regards
> >Rohit
> >
> >

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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