RE: [sv-bc] Errata: variable initializers don't match Verilog-2001

I believe the testbench section of SV depends on the currently defined
behavior, and initialization of variables other than their defaults is
testbench issue.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Friday, December 03, 2004 7:41 PM
To: sv-bc@eda.org; Brad.Pierce@synopsys.com
Subject: Re: [sv-bc] Errata: variable initializers don't match
Verilog-2001

For those who claim that the SystemVerilog requirement is "backward
compatible" with Verilog-2001, I have a question. Do you see any
problem with removing this requirement for now, leaving the Verilog-2001
rules, and possibly adding it back again later in a future revision?
After all, it will be just as backward compatible if it is added later.

If you believe that it would create a problem to release the standard
with the Verilog-2001 rules, and then add the restriction later, then
it creates the same problem to add the restriction now. Either way
you are adding this restriction that was not present in the earlier
standard.

On the other hand, any existing SystemVerilog implementation would still
be valid under the Verilog-2001 rules, so there would be no harm to them
from keeping the Verilog-2001 rules.

Steven Sharp
sharp@cadence.com
Received on Mon Dec 6 08:54:05 2004