RE: [sv-bc] DataTypes: friendly overview

From: Stuart Sutherland <stuart@sutherland-hdl.com>
Date: Thu Nov 11 2004 - 19:47:16 PST

Kathy,

I know this is late, but this is the first chance I've had for a while to
get back to e-mail. I have a suggestion for changing one paragraph. Its
not a critical change. Feel free to use all, some, or none from my
suggestion. The rest of the overview looks great. It would help, though to
add just a few more examples that show the new capabilities being added

> This extension for nets is limited to four-state data types
> because of schedule constraints in proposing LRM changes. We
> would have liked to propose two-state extensions as well. It
> is not our intent to preclude the extension of other data
> types to nets in the future.

The extensions to net types are syntactically and semantically backward
compatible with existing Verilog code. The extensions recommended at this
time are limited to supporting 4-state types with nets. The recommended
syntax and semantics have been carefully planned to allow future extensions,
such as support for nets with 2-state types and real types. These
additional extensions are not included at his time because of schedule
constraints.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
Received on Thu Nov 11 19:47:20 2004

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