RE: [sv-bc] DataTypes: Minor LRM edits

I would suggest --

  Unpacked structure and array data objects and unpacked structure
  and array constructors can all be used as aggregate expressions.

Please also consider if this new language added as part of 254 would
be impacted by the new proposal --

  The term simple bit vector type is used throughout this document to
  refer to the data types that can directly represent a one-dimensional
  packed array of bits. The packed vector types of Verilog-2001 are
  simple bit vector types, as are the integral types with predefined
  widths, such as byte. The SystemVerilog packed structure types and
  multidimensional packed array types are not simple bit vector types,
  but each is equivalent (see Section 5.8.2) to some simple bit vector
  type, to and from which it can be easily converted.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Brad
Pierce
Sent: Thursday, November 11, 2004 8:36 AM
To: Kathy McKinley; btf-dtype@boyd.com; sv-bc@eda.org
Subject: RE: [sv-bc] DataTypes: Minor LRM edits

The language suggested for 7.16 would need to be updated
to take into account the changes approved for erratum 254.

----------------------------------------------------------------------
SECTION 7.16

CHANGE:

Unpacked structure and array variables, literals, and
expressions can all be used as aggregate expressions.

TO:

Unpacked structure and array data objects, literals, and
                             ^^^^^^^^^^^^
expressions can all be used as aggregate expressions.

----------------------------------------------------------------------
Received on Thu Nov 11 09:48:22 2004