Dave,
The point about wires is that they have many more than four values, and
these new kind of wires need to connect to rtran gates.
That is why the 2/4 value distinction should be irrelevant. The wires
should only take on the "shape" and "naming" of the data type, not its
values. This is one justification for the wire <datatype> syntax in
Jonathan Bradford's proposal.
Regards,
Peter.
At 07:45 04/11/2004 -0800, Rich, Dave wrote:
>I feel that there is a big disconnect between the proposals from Cadence
>and SystemVerilog in that the 'unnamed 0,1,x,z data' type in the Cadence
>proposal is in deed what SystemVerilog called the 'reg datatype', and
>created a new name for that datatype, 'logic'. (Sometimes I get the funny
>feeling that we are debating Creationism versus Evolutionism)
>
>If we define the datatype on wires feature as simply a casting and type
>equivalence mechanism, then can limit the amount of changes needed to the LRM.
>
>
>Dave
>
>
>David Rich
>Verification Technologist
>Design Verification & Test Division
>Mentor Graphics Corporation
>dave_rich@mentor.com
>Office: 408 487-7206
>Cell: 510 589-2625
Received on Thu Nov 4 08:04:52 2004
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