Re: [sv-bc] DataTypes: the reg datatype

Dave,

Two comments:

1. There is no proposal 'from Cadence' but rather from the datatypes subgroup, even if its leader is from Cadence.

2. In SV, reg and logic imply variables with a specific resolution behavior different from that of nets.
Nets and regs/logics may have a common value set, but in SV currently, a net and a reg/logic are still very different creatures.

Which is the whole point of the proposal, that new datatypes were invented only for variables, but not for nets.

Shalom

On Thu, 4 Nov 2004, Rich, Dave wrote:

> I feel that there is a big disconnect between the proposals from Cadence and SystemVerilog in that the 'unnamed 0,1,x,z data' type in the Cadence proposal is in deed what SystemVerilog called the 'reg datatype', and created a new name for that datatype, 'logic'. (Sometimes I get the funny feeling that we are debating Creationism versus Evolutionism)
>
> If we define the datatype on wires feature as simply a casting and type equivalence mechanism, then can limit the amount of changes needed to the LRM.
>
>
> Dave
>
>
> David Rich
> Verification Technologist
> Design Verification & Test Division
> Mentor Graphics Corporation
> dave_rich@mentor.com
> Office:   408 487-7206
> Cell:     510 589-2625
>
>

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