Re: [sv-bc] DataTypes: The wone net type

Mark Hartoog wrote:

>I am somewhat confused by all this discussion. Is there some written material somewhere that describes what is being proposed?
>
>Single driver wires:
>
>What is the difference between a single driver wire and the logic data type?
>
>
 From a hardware modeling perspective a single driver wire is a circuit
node with only one process contributing current/voltage to it. In
Verilog the current/voltage contributed is of the symbolic type logic
(0,1,X or Z).

>Does port coercion apply to single driver wires?
>
>
Not sure what you mean by that. IMO ports just connect you to drivers
without modification (unless you are using VHDL - in which case bad
things can happen).

>Can a single driver wire ever be connected to multi-driver wire through
>a port? Does this imply that the combined wire can still have only a single
>drive or is this just illegal.
>
Again, from a modeling perspective if you connect a wire segment with a
single driver to another wire segment with other drivers you still only
have one circuit node, so it might be illegal if the drivers are not
compatible. The drivers are compatible if there is resolution function
that handles all the driver types: in Verilog the only resolved type is
logic.

Since SV also only provides a resolution function for logic all other
types can only be used in a single driver configuration on wires with
receivers (any process reading from the wire) of the same type.

>Can you have single driver wire inout ports?
>
>
No reason not to.

>2 state wires:
>
>What are the semantics of 2 state wires? Is there something written up some place?
>
>
The driver of a 2-state wire would only drive 1 or 0 (not X or Z). You
could have multiple 2-state drivers and do a 3-state resolution (to
0,1,X), but a 2-state resolution (to 0,1) could lead to major
verification errors, so you really don't want multiple 2-state drivers
on a wire with 2-state receivers. Currently I don't think you can mix
2-state and 4-state on a wire in SV, any 4-state assignment to a 2-state
object is coerced to 1 or 0 (without flagging it as an error - LRM p21 -
v. bad IMO).

It's best not to consider a wire itself as having a type: just view it
as interconnect between drivers and receivers which do have types.

>Data types on wires:
>
>I presume we are talking about struct, union and enum data types on wires. Is there a write up on this someplace? What syntax are people thinking about?
>
>
My personal opinion is that differentiation needs to be made between
datatypes that apply to a single (physical) wire and those meant as
bundles, e.g. you might want to use an enum (say 'H','L','h','l','z') to
represent multiple logic strengths and values on a single wire while
another enum (say 0xFF,0x3D,0x00) could be values on a control bus of 8
wires. Doing that probably requires adding a keyword (say "physical")
to the enum declaration, and drivers would be declared as per my
previous e-mail (http://www.eda.org/sv-bc/hm/2122.html). Defining
resolution functions and type conversion functions has not been
addressed yet.

>The enum data type variables are currently initialized to the first label. Are enum wires suppose to initialize to the first label? What value should a undriven enum wire go to?
>
Good question - maybe we need to add something like sticking default in
front of the value to use in the declaration.

Kev.

>Mark Hartoog
>700 E. Middlefield Road
>Mountain View, CA 94043
>650 584-5404
>markh@synopsys.com
>

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