Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

What was this referrring to?

Shalom

Steven Sharp wrote:

> This is well known, but has not been addressed in P1800.
>
> The semantics of variable initializers in SystemVerilog do not match the
> semantics defined in Verilog-2001. This is even explicitly acknowledged
> in the LRM.
>
> Steven Sharp
> sharp@cadence.com

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