>I believe that rule a above means that 'a.b.c' in the above example
>is an error.
If you assumed that once the first name component matched, it was
committed to only look in the module/scope/struct that matched, then yes.
However, that is not how hierarchical name resolution works in Verilog-XL,
or any implementation that matches it. If there is a match for the
start of the name, but the entire name is not matched, the upward search
continues. If there is a valid resolution anywhere, it will be found.
>I had heard that the IEEE Errata committee was looking at some open
>questions in hierarchical name resolution, and I do not currently have
>access to that information. I thought it was only related to issues with
>hierarchical names resolution and generate unrolling.
The rules you quoted need to be rewritten now that a module instantiation
can appear in a generate scope, not just at the module level. That is
not related to this issue.
Steven Sharp
sharp@cadence.com
Received on Wed Apr 7 16:41:39 2004
This archive was generated by hypermail 2.1.8 : Wed Apr 07 2004 - 16:41:44 PDT